Wafer inspection systems help a semiconductor manufacturer increase and maintain integrated circuit (IC) chip yields by detecting defects that occur during the manufacturing process. One purpose of inspection systems is to monitor whether a manufacturing process meets specifications. The inspection system indicates the problem and/or the source of the problem if the manufacturing process is outside the scope of established norms, which the semiconductor manufacturer can then address.
Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Thus, minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for the semiconductor manufacturer.
A semiconductor wafer may include multiple layers. A defect in one layer can impact manufacturing in layers that are later formed. A defect also can affect wafer yield regardless of the layer where the defect is located. The site with the defect in the earlier-formed or previously-formed layer can be referred to as a “pre-layer defect site.” It can be beneficial to monitor a defect and its impact on subsequent layers. Thus, semiconductor manufacturers may review pre-layer defect sites to improve high-volume production.
During semiconductor manufacturing, potential defects on each layer of a wafer can be found using a defect inspection tool, such as those using broad band plasma, laser scanning, or an electron beam. The defect locations are then reviewed under, for example, a scanning electron microscope (SEM) with high resolution imaging to confirm the existence of and/or type of defect.
It is difficult to monitor an impact to one or more subsequent layers caused by a defect on an earlier-formed layer. The images of various wafer layers are not aligned. Therefore, viewing a site of the defect in a layer with the coordinates from a previously-formed layer using, for example, an SEM tool can result in viewing the wrong region of a wafer. Deskewing layer images is not possible because the coordinate system may be different for different layers of the wafer. Users frequently guess whether, for example, an SEM image is the region that corresponds to the pre-layer defect site. Semiconductor manufacturers waste time confirming that a particular site in an image corresponds to the pre-layer defect site. This comparison is complicated because an approximate pattern match may only be possible for a few layers. If the images are more than a few layers apart, then the patterns in the image may be different enough that it may be impossible to confirm that the features in the image of the later-formed layer correspond to the location of the pre-layer defect.
Therefore, what is needed is an improved system and method to inspect wafers.